1. Field of the Invention
The present invention relates to a manufacturing method of a substrate for a semiconductor package, a manufacturing method of a semiconductor package, a substrate for a semiconductor package and a semiconductor package.
2. Description of the Related Art
Conventionally, a semiconductor package manufacturing method where a semiconductor device is sealed with resin is known as disclosed in Japanese Published Patent Application No. 2002-9196 (which is hereinafter called “Patent Document 1”). In the semiconductor manufacturing method, to begin with, a resist pattern layer with a predetermined pattern is formed on a conductive surface of a substrate. Then, conductive metal is electrodeposited on an exposed surface of the conductive surface of the substrate uncovered with the resist pattern layer so that a thickness of the conductive metal is over that of the resist pattern layer, by which a metal layer for semiconductor device mounting and electrode layers are respectively formed so as to have flared portions. After removing the resist pattern layer, a semiconductor device is mounted on the metal layer, and electrodes on the semiconductor device are electronically connected to the electrode layers by bonding wires. Finally, the semiconductor device mounting part is sealed with resin, and the substrate is removed. As a result, back surfaces of the metal layer and electrode layers are exposed, and a semiconductor device in a resin sealed body, a semiconductor package, is obtained.
According to the semiconductor package manufacturing method, because the flared portions are set to bite into the resin, binding power is improved due to the effect of biting. This helps important parts such as the metal layer and electrode layers stay in the resin sealed body without being pulled apart by sticking to the substrate, which can effectively prevent displacement and lack of the important parts. The semiconductor package manufacturing method also serves to ensure bonding strength after soldering the semiconductor device on a substrate for electronic components.
In addition, the characteristic flared shape formed around a whole circumference of a top edge of the metal layer and the electrode layers can prevent water from intruding from a backside of the semiconductor package through a boundary division between the metal layer or each of the electrode layers and the sealing resin layer, which can improve humidity resistance of the semiconductor package.
However, according to a configuration of Patent Document 1, because the electrodeposition is made over the resist pattern and not controlled by the resist pattern in a transverse direction, the electrodeposition process is susceptible to the effect of a distribution of current density, which makes it difficult to keep the length of the flared portions constant. This causes variation in the binding power between the electrode layers or metal layer and the resin. In addition, because the electrodeposition process is performed without any control by the resist pattern of its top surface, the top surface does not become flat, and a poor connection of a bonding wire tends to occur.
In recent years, because of semiconductor package downsizing advances, and semiconductor devices used for the semiconductor package have also tended to be miniaturized, an electrode layer of a substrate for a semiconductor device needs to be miniaturized and to realize high accuracy.
However, as disclosed in Patent Document 1, if the size of an electrode layer provided corresponding to a semiconductor device cannot be controlled with a high degree of accuracy, there is a concern that adapting miniaturization in the future may be impossible. Moreover, to obtain a certain biting effect between the electrode layers or metal layer and the resin, a length of the flared portion needs to be in a range of 5 to 20 μm. However, because a necessary thickness of the electrode layers and metal layer increases as the flared portion becomes longer, there is a concern that the semiconductor package manufacturing method disclosed in Patent Document 1 cannot be adapted to a tendency for a thinner semiconductor package.